The present invention relates to an editing apparatus and a generating method for physical conversion definition for generating physical conversion definition for converting a physical address of a memory cell in semiconductor memory into a logical address and an I/O number.
A semiconductor memory test system is a system to analyze a failure of each memory cell in semiconductor memory (hereinafter, this is simply called memory) by reading data from or writing data to each memory cell. In general, a semiconductor memory test system, as shown in FIG. 43, comprises a timing generator 110, a pattern generator 112, a waveform shaper 114, a logical comparator 116, and fail memory 118. An address and data generated by the pattern generator 112 are inputted to memory under test (MUT) after waveform-shaping by the waveform shaper 114. The logical comparator 116 compares data read from the MUT with an expected value outputted from the pattern generator 112, and judges pass or fail. The fail memory 118 saves fail information every address from a fail signal outputted from the logical comparator 116 and an address signal outputted from the pattern generator 112. A series of these operations are synchronized with a system clock inputted from the timing generator 110 into each unit.
In this manner, data relating to pass or fail of each memory cell of the MUT is saved in the fail memory 118 included in the semiconductor memory test system. Furthermore, failure analysis of the memory is performed by collecting the data and surveying contents of the data by a host system and the like.
By the way, physical arrangement of actual memory cells may be frequently different from address information inputted into memory (logical address). Therefore, even if the fail information saved in the fail memory 118, described above, is read, it is unknown which memory cell is defective.
A map showing a memory address where a failure is detected is called a xe2x80x9cfail bit map.xe2x80x9d A fail bit map is separated into a logical fail bit map and a physical fail bit map. The logical fail bit map is a four-dimensional fail bit map where logical addresses X, Y, and Z, and an I/O number are used as coordinates, and becomes a three-dimensional map in case the logical address Z is not used. This logical fail bit map can be obtained on the basis of fail information read from the fail memory 118 described above. The physical fail bit map is a two-dimensional fail bit map where physical addresses X and Y are used as coordinates, and is used when physical arrangement of a defective memory cell of the memory is confirmed. Since the failure analysis of the memory is usually performed with using this physical fail bit map, it becomes necessary to convert a logical fail bit map obtained by the fail memory 118 into a physical fail bit map.
In general, conversion of a logical fail bit map into a physical fail bit map is called xe2x80x9cphysical conversion.xe2x80x9d In a broad sense, it is called physical conversion to obtain a two-dimensional fail bit map with using a logical fail bit map and a physical conversion definition. Here, physical conversion definition means information for performing the physical conversion, the information which includes information for rapidly obtaining logical addresses and an I/O number from a physical address.
The physical conversion definition described above is performed with using an editing apparatus for physical conversion definition. Hereinafter, a generating method for physical conversion definition with using a conventional editing apparatus for physical conversion definition will be described.
(1) Setting of Address Parameters""
First, various address parameters are set. Concretely, the following parameters are set:
Size of horizontal logical address: HL
Size of vertical logical address: VL
I/O size: IO
Size of horizontal physical address: HP
Size of vertical physical address: VP
Axes of address
Here, respective values are set so that formula HLxc3x97VLxc3x97IO=HPxc3x97VP may hold. For example, HL=32, VL=16, IO=4, HP=64, and VP=32 are set, and the X-axis is set in the horizontal direction and the Y-axis is set in the vertical direction.
(2) Generation of Unit Layout
Next, a unit layout will be generated. This unit layout has three kinds of information, that is, width, height, and a position of an origin. Although a plurality of units whose sizes are different from each other are allowed, unit layouts besides a basic unit layout that is smallest are integer times as large as the basic unit layout.
FIGS. 44A and 44B are diagrams showing concrete examples of the unit layout. As for a unit layout xe2x80x9caxe2x80x9d shown in FIG. 44A, width is set at 24, height is at 4, and an origin is set on the upper right. In addition, as for a unit layout xe2x80x9cbxe2x80x9d shown in FIG. 44B, width is set at 8, height is at 4, and the origin is on the upper left.
(3) Generation of Block Layout
Next, a block layout is generated. The block layout is a layout where a plurality of units is arranged in a grid-like pattern, and a unit layout and an I/O number are assigned to each unit. It is not necessary that sizes of units included in a block are uniform so long as height or width of each row or each column is uniform.
FIGS. 45A and 45B are diagrams showing concrete examples of the block layout. A block layout A shown in FIG. 45A is set at 2 columns and 4 rows, and is composed by combining the unit layout xe2x80x9ca,xe2x80x9d shown in FIG. 44A, with the unit layout b, shown in FIG. 44B, in the horizontal direction and alternately combining unit layouts, which have I/O numbers 0 and 1, in the vertical direction. Therefore, the width of the block layout A is set at 32 and the height is at 16. Similarly, the width of a block layout B shown in FIG. 45B is set at 2 columns and 4 rows, and is composed by combining the unit layout xe2x80x9caxe2x80x9d, shown in FIG. 44A, with the unit layout xe2x80x9cbxe2x80x9d, shown in FIG. 44B, in the horizontal direction and alternately combining unit layouts, which have I/O numbers 2 and 3, in the vertical direction. Therefore, the width of the block layout B is set at 32 and the height is at 16.
(4) Generation of Main Layout
Next, a main layout is generated. The main layout is a layout where a plurality of blocks is arranged in a grid-like pattern, and a block layout and a sequence number are assigned to each block. Since sequence is meaningful for the sequence number, repeated numbers are not allowable. Block layouts assigned to blocks should have the same numbers of units in the horizontal direction and also in the vertical directions respectively, and furthermore, should have same numbers of memory cells in the horizontal direction and also in the vertical directions respectively.
FIG. 46 is a diagram showing a concrete example of a main layout. In the main layout shown in FIG. 46, respective block numbers in the horizontal and vertical directions are set at 2, and the main layout is composed of combining the block layouts A and B with the block layouts B and A. In addition, the sequence number xe2x80x9c1xe2x80x9d is set to the block layout A on the upper left, xe2x80x9c4xe2x80x9d is to the block layout A on the lower right, xe2x80x9c7xe2x80x9d is to the block layout B on the upper right, and xe2x80x9c9xe2x80x9d is to the block layout B on the lower left.
(5) Setting of Priority Direction in Address Assignment
Subsequently, either the horizontal direction or the vertical direction is set as the priority direction in address assignment.
After terminating the definition work by above operations (1) through (5), logical addresses X and Y are automatically assigned according to the following rules:
The origin of a physical address should be always on the upper left.
If the horizontal direction is X and the vertical direction is Y, the horizontal direction should be X and the vertical direction should be Y also in a physical address and a logical address. On the contrary, if the horizontal direction is Y and the vertical direction is X, the horizontal direction should be Y and the vertical direction should be X also in a physical address and a logical address.
A logical address should be sequentially assigned from a low address.
If the priority direction in address assignment is the horizontal direction, assignment of a logical address in the horizontal direction should be preferred. On the contrary, if the priority direction in address assignment is the vertical direction, assignment of a logical address in the vertical direction should be preferred.
When an address in the priority direction reaches the maximum value in the direction, the address in the priority direction should become 0 and an address in the non-priority direction should become a value obtained by adding one to the address lastly assigned.
A logical address should be sequentially assigned from the block having the smallest sequence number.
The logical address should be assigned from a unit on the upper left in a block.
If the priority direction in address assignment is the horizontal direction, logical addresses are assigned to units in a block in the order of priority of the horizontal direction. On the contrary, if the priority direction in address assignment is the vertical direction, logical addresses are assigned to units in a block in the order of priority of the vertical direction.
Addresses in a unit should be sequentially assigned from the origin of the unit.
FIG. 47 is an explanatory diagram showing a method for expressing logical addresses assigned in a unit. In the example shown in FIG. 47, with setting the origin on the upper right, a logical address in the horizontal direction, X is set in the range of 0-23, and a logical address in the vertical direction, Y is set in the range of 0-3. In addition, the I/O number corresponding to this unit is set at 0.
FIG. 48 is a diagram showing concrete example of assigning logical addresses in a main layout according to the rules described above. This shows an example of using the main layout shown in FIG. 46, block layouts shown in FIGS. 45A and 45B, and unit layouts shown in FIGS. 44A and 44B, and defining the horizontal direction as the priority direction in address assignment.
By the way, there arises the following problem in case of assigning logical addresses with using the conventional editing apparatus for physical conversion definition, which is described above:
(1) A user cannot set the order of address assignment in a block layout. For example, in the block layout having a sequence number xe2x80x9c1xe2x80x9d in the main layout shown in FIG. 48 (the block layout on the upper left), two unit layouts arranged in the first row are sequentially given logical addresses from the nearest unit to the upper left that is the origin. Therefore, it is not possible to sequentially assign a logical address from a unit on the upper right, on the contrary. In addition, if four units are there, it is not possible to assign logical addresses to central units after assigning logical addresses to both sides of units with overjumping the central units.
Owing to this, so as to perform the assignment of logical addresses that is equivalent to this, it is necessary, for example, to generate plenty of small blocks and to exchange the sequence of logical addresses with devising respective sequence numbers. Therefore, assignment work of logical addresses becomes complicated.
(2) Block definition where logical addresses are not consecutive in a block cannot be performed.
Since assignment is performed so that the logical addresses may be consecutive in a block, for example, as shown in FIG. 49, it is not possible to assign logical addresses so that the logical addresses may become consecutive in two blocks as a whole. Therefore, so as to perform the assignment of logical addresses that is equivalent to this, it is necessary to generate plenty of small blocks including one unit or a plurality of units where logical addresses are consecutive, and to exchange the sequence of logical addresses with devising respective sequence numbers. Therefore, assignment work of logical addresses becomes complicated.
(3) Block size should be uniform. For example, the main layout shown in FIG. 50 cannot be generated.
(4) Physical conversion definition where not all the logical addresses are included cannot be generated. In general, since physical conversion is complicated and needs long processing time, logical addresses corresponding to a part of memory cells in memory may not be consecutive if the physical conversion is performed for the part of memory cells. For example, if it is attempted to generate the main layout shown in FIG. 51, logical addresses in the horizontal direction, 50-6F are not included, and hence this runs counter to the rules described above. Therefore, it is not possible to generate physical conversion definition corresponding to such a main layout.
(5) An assignment rule at the time when the size of units included in a block is not uniform is not adequate. FIG. 52 is a diagram showing a state of assigning logical addresses when the priority direction in address assignment in the main layout shown in FIG. 48 is changed to the vertical direction. Assuming that address assignment is performed according to the sequence number shown in FIG. 46, first, a logical address is assigned to the block arranged on the upper left. With watching units corresponding to the I/O number xe2x80x9c0xe2x80x9d, logical addresses are assigned to units xe2x80x9caxe2x80x9d, xe2x80x9cbxe2x80x9d, xe2x80x9ccxe2x80x9d, and xe2x80x9cdxe2x80x9d in this order. In this manner, when logical addresses are assigned to four units, logical addresses in the vertical direction reach 15H that equals to the height of the block. Therefore, when the next assignment of a logical address is performed, an address in the vertical direction is assigned from the initial value after adding 1 to the last value of the logical address in horizontal direction. Therefore, logical addresses are assigned to a unit xe2x80x9cexe2x80x9d included in the block on the lower right according to the sequence number. Nevertheless, if the logical address in the horizontal direction is made to be 8 by adding 1 to the last value xe2x80x9c7,xe2x80x9d this logical address becomes equal to the logical address assigned in the unit xe2x80x9ca,xe2x80x9d and hence an error arises. In this manner, since combination of units whose sizes are irregular is allowed, the contradictory assignment of logical addresses may be performed.
(6) Although it is necessary to set a sequence number defining the sequence of each block before assignment of logical addresses, it is difficult to adequately set this sequence number. Therefore, a user not matured needs long setting time of the sequence number and needs to repeat assignment of logical addresses by changing sequence numbers many times, and hence complexity increases. In particular, since large capacity of memory is brought to market recently, also, the number of blocks in a main layout has the tendency of sharply increasing. Therefore, since a user needs long time for the setting work of the sequence number, the user loses his/her eager for generating the physical conversion definition.
(7) Since the origin of the physical address is fixed on the upper left, it is necessary to devise the sequence number of each block by decreasing the size of each block.
In this manner, there are problems that working efficiency decreases due to many restrictions if the physical conversion definition is generated with using the conventional method. Therefore, a method that has few restrictions and can increase working efficiency has been desired.
The present invention is created in consideration of these points and is to provide an editing apparatus and a generating method for physical conversion definition that have few restrictions and can increase working efficiency.
An editing apparatus for physical conversion definition according to a preferable embodiment of the present invention generates layouts through the following procedure. Thus, address parameter setting means specifies address parameters including information relating to the setup contents of physical addresses and logical addresses of semiconductor memory. Furthermore, layout means sets a plurality of elements whose structural unit is one memory cell or a plurality of memory cells, and specifies a logical address to each of these elements. Therefore, by directly specifying the logical address of each element included in the layout, it is possible to generate the physical conversion definition defining the relation between the physical address and logical address. Therefore, it is not necessary to perform complicated setting such as presetting of a sequence number specifying the sequence of assignment of logical addresses like a conventional apparatus. Hence, restrictions are few, and it is possible to increase working efficiency at the time when the physical conversion definition is generated.
In addition, it is preferable to construct the layouts, described above, in a hierarchical structure and to make each element included in the lowest layout correspond to a memory cell in the semiconductor memory. Usually, since correspondence of a physical address of the semiconductor memory to a logical address is repeated in many cases with making a predetermined range a unit. Hence, by generating layouts in a hierarchical structure with making this predetermined range a unit, regularity becomes clear. Therefore, since specification of each bit in a logical address becomes easy, working efficiency can be further increased. In particular, if logical addresses of a plurality of layouts that are included in the same hierarchy have the same regularity, it becomes possible to generate another layout by inverting predetermined bits in a logical address of a certain layout instead of individually generating each layout. Hence, it becomes possible to reduce workload.
In addition, it is preferable that the layout generating means described above has a function of specifying the number of elements in a layout and a function of specifying a logical address of an element, which is selected, every bit. This is because it is possible to perform generation work of the physical conversion definition by specifying the optimum number of elements every semiconductor memory since it is possible to specify an optional number of elements on the basis of the regularity of the logical addresses. Furthermore, since it is possible to specify a logical address every bit, it is possible to optionally specify the sequence of logical addresses and the like, and hence it becomes possible to further freely set logical addresses.
Moreover, it is preferable to generate layouts by the layout generating means according to predetermined rules for deciding the physical conversion definition. By performing the uniform generating work of layouts according to the predetermined rules, it is possible to increase the working efficiency and to reduce errors and the like arising at the time of performing the subsequent physical conversion.